1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus including a through silicon via (TSV) are provided. The TSV may be stacked with other chips.
2. Related Art
There has been provided a three dimensional (3D) semiconductor apparatus, with which a plurality of chips are stacked and packaged in a single package, for higher integration thereof. More recent uses include a through silicon via (TSV), with which the stacked chips are penetrated and electrically connected through a silicon via.
FIG. 1 is a schematic diagram illustrating a semiconductor chip, where a TSV is formed.
Referring to FIG. 1, the TSV 12 is formed to pass through the semiconductor chip 11. The semiconductor chip 11 is penetrated to form a via hole and a silicon insulating layer 13 is formed around the via hole. A conductive material 14 is then filled in the via hole, thereby forming a through electrode or a through line capable of transferring an electrical signal.
A metal layer 15 is formed over the TSV 12. The metal layer 15 covers an upper portion of the TSV 12 and is electrically coupled to internal circuits (not shown) of the semiconductor chip 11. Therefore, the internal circuits of the semiconductor chip 11 receive a signal from the TSV 12 or transfer a signal to the TSV 12 through the metal layer 15.
A bump 16 is stacked over the metal layer 15 and coupled to another TSV of another semiconductor chip. Therefore, the semiconductor chip 11 can be electrically coupled to and stacked with another semiconductor chip.